The active geometries of transistors may be joined together to eliminate the shallow trench isolation to reduce area and reduce cost in scaled-down technologies. For example two transistors 16 and 18, with gates 24 and 26, with active areas 20 and 22, having different transistor widths 21 and 23, respectively, as shown in FIG. 1 may be joined together as shown in FIGS. 2A and 2B. By joining the two active areas 20 and 22 together, the space 28 between the active areas 20 and 22 which is filled with shallow trench isolation (STI) field oxide may be eliminated significantly reducing the area of the two series transistors 16 and 18. Dummy gates 30 typically surround the transistor gates, 24 and 26, at a fixed pitch to improve patterning of the gates 24 and 26 and also to control the profile of the gates 24 and 26 during plasma etch.
In FIG. 2A two active area jogs, 32 and 34, are formed in the active areas 20 and 22 where the active area 20 with the larger width 21 transitions to the active area 22 with the lesser width 23.
In FIG. 2B one active area jog, 36 is formed in the active areas 20 and 22 where the wide active area 20 transitions to the narrow active area 22.
One problem with the transistor structure with joined active geometries is that the active overlap of the wide transistor is no longer uniform across the width of the wide transistor. In FIG. 1, active area overlaps 23 and 27 of the active area 20 adjacent to the gate 24 are of uniform width across the length of the transistor so series resistance due to the active area 20 is uniform. In FIG. 2B, the active area overlap 37 of the active area 20 adjacent to the gate 24 at the active area jog 36 is significantly less than that active area overlap 33 of the active area 22 adjacent to the gate 24 below the active area jog 36. The narrowness of the active area overlap 37 may also result in poor silicide formation additionally increasing series resistance and degrading the transistor 16 performance.
In scaled-down technologies, the close proximity of the active area jog 37 to the gate 24 of the transistor 16 has a pronounced impact on the width 21 of the transistor 16 due to photolithographic effects.
In FIG. 3 the active area jog 36 is placed midway between the gate 46 of the transistor 16 with the larger width 21 and the gate 48 of the transistor 18 with the lesser width 23. The active area overlap 44 of the active area 20 adjacent to the gate 46 at the active area jog 36 is about equal to active area spacing 42 between the active area jog 36 and the gate 48.
The percentage change in channel width of the transistor 16 as a function of the jog height 40 of the active area jog 36 is shown by plot 60 in FIG. 5. As is shown in the graph, when the jog height 40 exceeds about 20 nm, the percentage change in transistor width due to lithographic effects exceeds about 15%. Typically circuit simulators do not take this variation into account. Not taking this much variation into account may cause the circuit to fail.
To reduce the variation due to photolithographic effects and to reduce the difference in the active area overlap of a wide transistor gate at the active area jog and the active area overlap of the wide transistor gate below the active area jog, the active area jog may be placed midway between the wide and narrow transistor gates. Instead the active area jog may be moved closer to the narrow width transistor to increase the active area overlap of the wide width transistor gate as shown in FIG. 4. In FIG. 4, the active area overlap 52 of the active area 20 adjacent to the gate 56 of the transistor 16 with the larger width 21 is about double the active area spacing 50 between the active area jog 36 and the gate 58 of the transistor 18 with the lesser width 23.
The percentage change in channel width 53 of the transistor 16 with the larger width 21 as a function of the jog height of the active area jog 36 is shown by plot 62 in FIG. 5. The percentage change in channel width 53 of the transistor 16 is defined as the change in channel width 57 divided by the width 21 of the active area 20, times 100. As is shown in the graph, when the jog height exceeds about 20 nm, the change in transistor width due to lithographic effects exceeds about 11%. Typically circuit simulators do not take this variation into account. Not taking this much variation into account may cause the circuit to fail.
Scaled-down technologies often rely on strain engineering to boost the carrier mobility in the channel. Electron mobility in the channel of an NFET may be enhanced by applying tensile stress to the NFET channel and hole mobility in the channel of a PFET may be enhanced by applying compressive stress to the PFET channel.
For example, in the case of silicon substrates, p-channel field effect transistors (PFETS) are typically fabricated on substrates with a <100> crystallographic surface orientation. In <100> silicon the mobility of holes, which are the majority carriers in PFET can be increased by applying a compressive longitudinal stress to the channel. A compressive longitudinal stress is typically applied to the channel of a PFET by etching silicon from the source and drain regions and replacing it with epitaxially grown SiGe. Crystalline SiGe has a larger lattice constant than silicon and consequently causes deformation of the silicon matrix that, in turn, compresses the silicon in the channel region. Compression of the silicon lattice in the channel causes a separation of the light and heavy hole bands with a resulting enhancement of the low-field hole mobility. The increased hole mobility improves the PFET performance.
Because the lattice constant of single crystal SiGe is larger than the lattice constant of single crystal Si, the SiGe is under significant compressive stress during epitaxial crystal growth. FIG. 6 depicts an integrated circuit with substrate 70 and STI field oxide 84 in the substrate 70 and gates 76 on the substrate 70 and STI field oxide 84. The gates 76 have transistor sidewalls 74 on lateral surfaces. SiGe regions 78 are formed in the substrate adjacent to the transistor sidewalls 74 to form source and drain regions of transistors in the integrated circuit. To minimize stress, it is thermodynamically favorable to form facets 80 as is shown in FIG. 6. These facets 80 typically are formed at an interface of the SiGe regions 78 and the STI field oxide 84. These facets reduce the amount of SiGe next to the transistor channel region 82 and therefore reduce the stress applied to the channel of the transistor that lies beneath the transistor gate 76. Thus when facets 80 are formed the performance of the PFET is degraded. In addition, faceting may result in an increase in threading dislocations and an increase in diode leakage. The SiGe regions 78 may be formed next to the transistor sidewalls 74 as shown in FIG. 6 or may be formed next to the transistor gate 76 prior to formation of the transistor sidewalls 74. Forming SiGe in closer proximity to the channel region increases the compressive stress applied to the channel.
FIG. 7 depicts an integrated circuit with substrate 70 and STI field oxide 84 in the substrate 70 and gate 76 on the substrate 70. The gate 76 has transistor sidewalls 74 on lateral surfaces. SiGe regions 78 are formed in the substrate adjacent to the transistor sidewalls 74 to form source and drain regions of a transistor in the integrated circuit. As shown in FIG. 7, one method of eliminating the SiGe/STI dielectric interface where faceting typically occurs is to form a dummy gate 92 overlying the STI field oxide/substrate interface 90. This prevents SiGe from coming into contact with the STI field oxide where faceting typically occurs.
Transistor structures with active jogs such as are shown in FIGS. 2A and 2B are especially problematic for PFETS with epitaxial SiGe stress enhancement and for NFETS with epitaxial SiC stress enhancement. Faceting which reduces stress enhancement decreasing transistor performance and increased threading dislocations which cause excessive diode leakage are commonly formed during epitaxial growth of SiGe or SiC next to jogs. Consequently design rules which forbid active jogs when stress enhancement is to be used are commonly used. These design rules result in increased transistor area and increased cost.